MIPS atomic memory operations
zhaixiang at loongson.cn
Thu Jan 17 09:38:34 UTC 2019
在 2019/1/16 下午5:44, Robert O'Callahan 写道:
> On Wed, Jan 16, 2019 at 10:22 PM Leslie Zhai <zhaixiang at loongson.cn
> <mailto:zhaixiang at loongson.cn>> wrote:
> I simply read your technical report and noticed that porting RR to
> failed due to ARM atomic memory operations use such as LL/SC
> "load-linked/store-conditional" instructions, perhaps it is the same
> issue for OpenJDK MIPS porting. For example, emit_compare_and_swap
> The same LL/SC "story"...
> Yes, it is very likely MIPS has the same problem.
> Maybe you could convince the hardware designers to add a feature to
> optionally generate a synchronous trap when a SC instruction fails.
> That would be enough to make rr work.
The hardware designers are *upstairs* on us.
> Hi Robert,
> Please teach me how to modify rr's design philosophy? It is sure
> a lot
> of work but balanced cost/benefit for hunting the self-modifying
> bug when porting OpenJDK HotSpot JIT compilers to MIPS backend.
> I'm sure porting the Hotspot JIT to MIPS creates some very hard bugs,
> but I think even if you found a way around the LL/SC problem, porting
> rr to MIPS would be a lot of work. I guess it would take at least six
> months. It's unlikely it would be worth it just to fix Hotspot JIT bugs.
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