MIPS atomic memory operations

Leslie Zhai zhaixiang at loongson.cn
Wed Jan 16 09:21:53 UTC 2019


Hi Kyle,

Thanks for your kind response! 
https://github.com/mozilla/rr/issues/1373#issuecomment-454647735

I simply read your technical report and noticed that porting RR to ARM 
failed due to ARM atomic memory operations use such as LL/SC 
"load-linked/store-conditional" instructions, perhaps it is the same 
issue for OpenJDK MIPS porting.  For example, emit_compare_and_swap 
http://hg.loongnix.org/jdk8-mips64-public/hotspot/file/dca904de5de5/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp#l3912

The same LL/SC "story"... 
http://hg.loongnix.org/jdk8-mips64-public/hotspot/file/dca904de5de5/src/cpu/mips/vm/macroAssembler_mips.cpp#l2692

Hi Robert,

Please teach me how to modify rr's design philosophy?  It is sure a lot 
of work but balanced cost/benefit for hunting the self-modifying code's 
bug when porting OpenJDK HotSpot JIT compilers to MIPS backend.

Thanks,

Leslie Zhai





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