MIPS atomic memory operations
zhaixiang at loongson.cn
Wed Jan 16 09:21:53 UTC 2019
Thanks for your kind response!
I simply read your technical report and noticed that porting RR to ARM
failed due to ARM atomic memory operations use such as LL/SC
"load-linked/store-conditional" instructions, perhaps it is the same
issue for OpenJDK MIPS porting. For example, emit_compare_and_swap
The same LL/SC "story"...
Please teach me how to modify rr's design philosophy? It is sure a lot
of work but balanced cost/benefit for hunting the self-modifying code's
bug when porting OpenJDK HotSpot JIT compilers to MIPS backend.
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